`include "cpu_def.vh"

module hazard(
  input stall_req_de ,
  input stall_req_ex ,
  input stall_req_wb ,
  input de_valid,
  input ex_valid,
  input wb_valid,
  
  input flush_req_ex ,
  input flush_req_wb ,

  output [2:0] stall,
  output [2:0] flush
);

  assign stall[2] = stall_req_wb;
  assign stall[1] = stall_req_ex || stall[2] && wb_valid && ex_valid;
  assign stall[0] = stall_req_de || stall[1] && ex_valid && de_valid;

  assign flush[2] = flush_req_wb || stall_req_ex && !stall[2];
  assign flush[1] = flush_req_wb || flush_req_ex && !stall[2] || stall_req_de && !stall[1];
  // assign flush[0] = flush_req_wb || flush_req_ex;
  assign flush[0] = 1'b0;

endmodule
